Modern integrated circuits use conductive interconnect layers to connect individual devices on a chip and/or to send and/or receive signals external to the device. Common types of interconnect layers include copper and copper alloy interconnect lines coupled to individual devices, including other interconnect lines by interconnect through vias. It is not uncommon for an integrated circuit to have multiple levels of interconnections. For example, two or more interconnect layers may be separated from each other by dielectric materials. The dielectric layers separating interconnect levels are commonly referred to as an interlayer dielectric (ILD).
As these interconnect layers are manufactured with interconnect lines having smaller pitches in order to accommodate the need for smaller chips, it becomes increasingly difficult to properly align the vias with the desired interconnect layer. In particular, during manufacturing, the location of the via edges with respect to the interconnect layer or line it is to contact may be misaligned due to natural manufacturing variation. A via however, must allow for connection of one interconnect line of one interconnect layer to the desired underlying layer or line without erroneously connecting to a different interconnect layer or line. If the via is misaligned and contacts the wrong metal feature, the chip may short circuit resulting in degraded electrical performance. One solution to address this issue is to reduce the via size, for example, by making the via narrower. However, reducing the via size results in an increase in resistance and reduces the yield during manufacturing.